U.S. Pat. No. 6,818,464, assigned to the assignee of this application, discloses a double-sided etching technique for providing a semiconductor structure with one or more through-holes that are sealed hermetically by a feed-through metallization process. The feed-through metallization process may include using an electroplating technique. The semiconductor structure can be used, for example, as a lid for a package that encapsulates an opto-electronic or other device or an integrated circuit. The through-wafer electrical interconnections may provide electrical contact, for example, from outside the package to the device or circuit encapsulated within the package.
According to a particular embodiment disclosed in the foregoing patent, the double-sided etching technique is performed on a silicon wafer that includes a buried etch-stop layer. Although the through-wafer electrical interconnections can be obtained satisfactorily, inclusion of a buried etch-stop layer in the semiconductor wafer can be expensive. Likewise, use of electroplating techniques to form the feed-through metallization can be expensive.
The present invention can obviate the need for such a buried etch-stop layer and does not require use of electroplating techniques to form the feed-through metallization.